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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH4S64CWZTJ is 4194304-word by 64-bit Synchronous DRAM module. This consists of sixteen industry standard 2Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules.
85pin
1pin
94pin 95pin
10pin 11pin
FEATURES
Frequency -12 -15 83MHz 67MHz CLK Access Time 8.5ns 9.5ns
Back side
Front side
-1 Utilizes industry standard 2M x 8 Synchronous DRAMs 100MH 8.5n 0 TSOP and industry standard EEPROM in TSSOP z s
168-pin (84-pin dual in-line package)
124pin 125pin
40pin 41pin
single 3.3V0.3V power supply Clock frequency 83MHz/67MHz Fully synchronous operation referenced to clock rising edge Dual bank operation controlled by BA(Bank Address) /CAS latency- 2/3/4(programmable) Burst length- 1/4(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface
168pin 84pin
APPLICATION
main memory or graphic memory in computer systems
SPD table
Byte No.
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 126 127
06 01 05 02 04 01 01 83 06 06 01 05 02 04 01 01 66 06
MH4S64CWZTJ-12 80 08 04 0C 09 02 MH4S64CWZTJ-15 80 08 04 0C 09 02
40 00 01 C0 85 00 80 00 40 00 01 F0 95 00 80 00
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 1 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
PIN NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC NC VSS NC NC VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA NC VDD CK1 NC PIN NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAME VSS CKE /S3 DQMB6 DQMB7 NC VDD NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VDD
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PIN NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC NC VSS NC NC VDD /WE0 DQMB0 DQMB1 /S0 NC VSS A0 A2 A4 A6 A8 A10 NC VDD VDD CK0
PIN NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
PIN NAME VSS NC /S2 DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VDD
NC = No Connection
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 2 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
Block Diagram
CK0 /S1 /S0 DQMB0
DQM /CS CK0 DQM /CS CK0
DQMB4
DQM /CS CK0 DQM /CS CK0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 D12 I/O 5 I/O 6 I/O 7
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CK1 /S3 /S2 DQMB2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D13
DQMB6
DQM /CS CK0 DQM /CS CK0 DQM /CS CK0 DQM /CS CK0
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 D14 I/O 6 I/O 7
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQM /CS CK0
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CKE /RAS /CAS /WE BA,A<10:0> Vcc Vss
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 D11 I/O 5 I/O 6 I/O 7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
D0 - D15 D0 - D15 D0 - D15 D0 - D15 D0 - D15 D0 - D15 D0 - D15
SERIAL PD SCL A0 A1 A2 SA0 SA1 SA2 SDA
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Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
CK (CK0 & CK1) Input Master Clock:All other inputs are referenced to the rising edge of CK Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. Chip Select: When /S is high,any command means No Operation. Combination of /RAS,/CAS,/WE defines basic commands. A0-10 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-10.The Column Address is specified by A0-8.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA is not simply BA.BA specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands
CKE
Input
/S (/S0 ~ /S3) /RAS,/CAS,/WE
Input Input
A0-10
Input
BA
Input
DQ0-63
Data In and Data out are referenced to the rising edge of Input/Output CK Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Input
Vdd,Vss SLA SDA SA0-3
Power Supply Power Supply for the memory mounted module. Input Output Input Serial clock for serial PD Serial data for serial PD Address input for serial PD
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 4 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH4S64CWZTJ provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK /S /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 5 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Adress Entry & Bank Activate Single Bank Precharge Precharge All Bank Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CK n-1 H H H H H H CK n X X X X X X /S H L L L L L /RAS /CAS X H L L L LH X H H H H H /WE X H H L L L BA X X V V V V A10 X X V L H L A0-9 X X V X X V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
X H L H H X X
L L L H L L L
H HL L LX H H L
L L L X H H L
H H H X H L L
V X X X X X L
H X X X X X L
V X X X X X V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0053-0.2
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Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State IDLE /S H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS /CAS X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L L L L L H L L L L L H H L L L H L H L BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 ACT PRE/PREA REFA MRS Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
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Aug.8.1996
Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /S H L L L /RAS /CAS X X H H H H H L /WE Address X X H L H X BA BA,CA,A10 Command DESEL NOP TBST Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst
Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add
WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS
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MITSUBISHI ELECTRIC ( 8 / 44 )
Aug.8.1996
Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING /S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
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Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING /S H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0053-0.2
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Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
Current State SELF REFRESH*1 CK n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CK n X H H H H H L X H L H L L L L L L X H L H L /S X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend Action
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only form the All banks idle State. 3. Must be legal command.
MIT-DS-0053-0.2
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Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX MRS
MODE REGISTER SET
REFA
IDLE
AUTO REFRESH
CKEL
CLK SUSPEND
CKEL CKEH
CKEH ACT
POWER DOWN
ROW ACTIVE
WRITE WRITEA READA READ WRITE READ
CKEL
CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
MIT-DS-0053-0.2
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Aug.8.1996
Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500E s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CK /S BA A10 0 0 A9 0 A8 0 A7 0 A6 A5 A4 A3 A2 A1 A0 /RAS /CAS LTMODE BT BL /WE BA, A10 -A0 BL 000 001 010 011 100 101 110 111 0 1 BT= 0 1 2 4 8 R R R R SEQUENTIAL INTERLEAVED
V
LATENCY MODE
CL 000 001 010 011 100 101 110 111
/CAS LATENCY R 1 2 3 4 R R R
BURST LENGTH
BT= 1 1 2 4 8 R R R R
BURST TYPE
R:Reserved for Future Use
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Aug.8.1996
Preliminary Spec.
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MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
CK Command Address DQ CL= 3 BL= 4 /CAS Latency
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 14 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank address(BA). A row is indicated by the row address A10-0. The minimum activation interval between one bank and the other bank is tRRD. PRECHARGE The PRE command deactivates indicated by BA. When both banks are active, the precharge all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CK Command A0-9 A10 BA DQ
ACT tRRD Xa tRCD Xa 0 Xb 1 0 0 Qa0 Qa1 Qa2 Qa3 1 Xb 1 Xb Y ACT READ tRAS PRE tRP Xb ACT
Precharge all
READ After tRCD from the bank activation, a READ command can be issued. 1st output date is available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8) by interleaving the dual banks. When A10 is high at a READ command, the auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge start timing depends on /CAD Latency. The next ACT command can be issued after tRP from the internal precharge timing.
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 15 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
Dual Bank Interleaving READ (BL=4, CL=3)
CK Command A0-9 A10 BA DQ
/CAS latency ACT tRCD Xa Xa 0 Y 0 0 Xb Xb 1 Qa0 Y 0 1 Qa1 0 0 Qa2 Qa3 Qb0 Qb1 Qb2 READ ACT READ PRE
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK Command A0-9 A10 BA DQ
ACT tRCD Xa Xa 0 Y 1 0 Qa0 Qa1 Qa2 Qa3 READ tRP Xa Xa 0 ACT
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CK Command CL=4 CL=3 CL=2 DQ DQ DQ
Qa0 Qa0 Qa1 ACT READ Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa2 Qa3 Qa3
Internal Precharge Start Timing MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 16 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous input data (in case of BL=8) by interleaving the dual banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CK Command A0-9 A10 BA DQ
ACT tRCD Xa Xa 0 Y 0 0 Da0 Xb Xb 1 Da1 Da2 Da3 Write ACT tRCD Y tWR 0 1 Db0 0 0 Db1 Db2 Db3 Write PRE
Burst Length
WRITE with Auto-Precharge (BL=4)
CK Command A0-9 A10 BA DQ
ACT tRCD Xa Xa 0 Y 1 0 tWR Da0 Da1 Da2 Da3 Write tRP Xa Xa 0 ACT
Internal precharge begins
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 17 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read option can be interrupted by new read of the same or the other bank. MH4S64CTJ allows random column access. READ to READ interval is minimum 1 CK Read Interrupted by Read (BL=4, CL=3)
CK Command A0-9 A10 BA DQ
READ READ Yi 0 0 Yj 0 0 READ Yk 0 1 Qai0 Qaj0 READ Yl 0 0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3)
CK Command A0-9 A10 BA DQMB0-7 Q D
Qai0 Daj0 Daj1 Daj2 Daj3 READ Yi 0 0 Write Yj 0 0
DQM control
Write control
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 18 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same or the other bank. Read to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on the /CAS Latency. The figure below shows examples, when the dataout is terminated. Read Interrupted by Precharge (BL=4)
CK
Command DQ
READ
PRE Q0 Q1 Q2 Q3
CL=4
Command DQ
READ PRE Q0 Q1
Command DQ
READ Q0
PRE Q1 Q2 Q3
CL=3
Command DQ
READ PRE Q0 Q1
Command DQ
READ Q0 Q1
PRE Q2 Q3
CL=2
Command DQ
READ PRE Q0 Q1
Comman d DQ
REA D Q 0 REA D Q 0 Q 1 PR E Q 1 Q 2
PRE Q 3
CL= 1
Comman d DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 19 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ] Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TERM interval is minimum 1 CK. The figure below shows examples, when the dataout is terminated. Read Interrupted by Burst Terminate (BL=4)
CK
Command DQ Command
READ Q0
TERM Q1 Q2 Q3
READ
TERM Q0 Q1 Q2
CL=3
DQ Command DQ
READ TERM Q0
Command DQ Command
READ Q0 Q1
TERM Q2 Q3
READ Q0
TERM Q1 Q2
CL=2
DQ Command DQ
READ TERM Q0
Comman d DQ
REA D Q 0 REA D TERM Q 0 Q 1 Q 2
TERM Q 3
CL= 1
Comman d DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 20 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CK. Write Interrupted by Write (BL=4)
CK Command A0-9 A10 BA DQ
Write Write Yi 0 0 Dai0 Yj 0 0 Daj0 Daj1 Write Yk 0 1 Write Yl 0 0 Dal1 Dal2 Dal3
Dbk0 Dbk1 Dbk2 Dal0
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3)
CK Command A0-9 A10 BA DQMB0-7 DQ
Dai0 Qaj0 Qaj1 Dak0 Dak1 Qbl0 Write READ Yi 0 0 Yj 0 0 Write Yk 0 0 READ Yl 0 1
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 21 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Because the write recovery time(tWR) is required between the last input data and the next PRE, 3rd data should be masked with DQMB0-7 shown as below. Write Interrupted by Precharge (BL=4)
CK Command A0-9 A10 BA DQMB0-7 DQ
Dai0 Dai1 Write tWR Yi 0 0 0 0 PRE tRP Xb Xb 0 ACT
This data should be masked to satisfy tWR requirement.
[ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. The figure below shows the case 3 words of data are written. Random column access is allowed. WRITE to TERM interval is minimum 1 CK. Write Interrupted by Burst Terminate (BL=4)
CK Command A0-9 A10 BA DQMB0-7 DQ
Dai0 Dai1 Dai2 Write Yi 0 0 TERM
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 22 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA cycle within 64ms refresh 16Mbit memory cells. The auto-refresh is performed on each bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks must be in the idle state. Additional commands must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CK /S NOP or DESLECT /RAS /CAS /WE CKE A0-10 BA
minimum tRC
Auto Refresh on Bank 0
Auto Refresh on Bank 1
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 23 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs including CK0 are disabled and ignored, and power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK0 inputs, asserting DESEL or NOP command and then asserting CKE(REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted till then. Self-Refresh
CK
Stable CK
/S /RAS /CAS /WE CKE
NOP
new command
A0-10 BA
X 0
Self Refresh Entry
Self Refresh Exit
minimum tRC for recovery
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 24 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored.
CK (ext.CLK) CKE
int.CLK
Power Down by CKE
CK CKE Command
PRE Standby Power Down
NOP NOP NOP NOP NOP NOP NOP
CKE Command
ACT
Active Power Down
NOP NOP NOP NOP NOP NOP NOP
DQ Suspend by CKE
CK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 25 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL DQMB0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to write mask latency is 0. During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z latency is 2. DQM Function
CK Command DQMB0-7
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 26 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25C Condition with respect to Vss with respect to Vss with respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 16 0 ~ 70 -45 ~ 100 Unit V V V mA W C C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted) Symbol Vdd Vss VIH VIL Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 2.0 -0.3 Limits Typ. 3.3 0 Max. 3.6 0 Vdd+0.3 0.8 Unit V V V V
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CK0 pin Input Capacitance, I/O pin Test Condition VI = Vss f=1MHz Vi=25mVrms Limits(max.) 65 65 65 22 Unit pF pF pF pF
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 27 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Symbol Icc1s Icc1d Icc2h Icc2l Icc3 Icc4 Icc5 Icc6 Parameter Test Condition Limits(max) Unit -12 -15 704 568 mA 944 768 mA 288 256 mA 32 32 mA 408 368 mA 624 528 mA 960 800 mA 16 16 mA
-1 0 operating current, single bank tRC=min.tCLK=min, BL=1, CL=3 64 0 operating current, dual bank tRC=min.tCLK=min, BL=1, CL=3 960 standby current, CKE=H both banks idle(discrete), tCLK=min, CKE=H 16 01 standby current, CKE=L both banks idle(discrete), tCLK=min, CKE=L both banks active(discrete), tCLK=min, CKE=H 6 active standby current 28 0 burst current tCLK=min, BL=4, CL=3, 1 bank idle 52 0 auto-refresh current tRC=min, tCLK=min 52 08 self-refresh current CKE <0.2V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) VOH(AC IOZ ) VOL(AC) Ii IOZ Ii Parameter High-Level Output Voltage(DC) Low-Level Output Voltage(DC) Off-stare Output Current High-Level Output Voltage(AC) Input Current Low-Level Output Voltage(AC) Off-stare Output Current Input Current Limits Min. Max. IOH=-2mA 2.4 IOL=2mA 0.4 Q floating CL=50pF, VO=0 ~ Vdd -20 2 20 IOH=-2mA -160 160 VIH=0 ~ Vdd+0.3V CL=50pF, 0.8 IOL=2mA VO=0 A Vdd -1 Q floating 1 0 0 VIH=0 A Vdd+0.3V -8 8 0 0 Test Condition Unit V V uA V uA V EA E A
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 28 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Limits -12 -15 Unit Min. Max. Min. Max. ns 30 30 ns 15 20 ns 12 15 5 5 ns 5 5 ns 1 1 1 10 ns 0 3 3 ns 2 2 ns 100 120 ns 30 30 ns 70 10000 80 10000 ns 30 40 ns 12 15 ns 24 30 ns 24 30 ns 12 15 ns 65.6 65.6 ms
Symbol Parameter tCLK tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tPDE tREF CK cycle time CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley time Mode Register Set Cycle time Power Down Exit time Refresh Interval time
-1 Min 0 .3 0 1 5 1 05 5 1 3 2 9 0 3 0 6 0 3 0 1 0 2 0 2 0 1 0
Max. CL=1 CL=2 CL=3
1 0
1000 0
65.6
CK
1.4V
Any AC timing is referenced to the input
Signal
1.4V
signal crossing through 1.4V.
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 29 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter CL= 1 CL= 2 CL= 3 CL= 1 3 0 3 8 -1 0 Min. Limits -12 -15 Uni Min. Max. Min. Max. t 27 30 ns 9.5 12 ns 8.5 9.5 ns 24.5 30 ns 54.5 60 ns 3 0 3 8 3 0 3 10 ns ns ns
tAC tCAC tRAC tOH tOLZ tOHZ
Access time from CK Column Access Time Row Access Time Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK
Max. CL=1 2 79 CL=2 CL=3 8 2 4 5 4 CL=1
Output Load Condition
50
VTT=1.4V
CK
1.4V
DQ VOUT 50pF Output Timing Measurement Reference Point
1.4V
CK
1.4V
DQ
tAC tOH
tOHZ
1.4V
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 30 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
WRITE CYCLE (single bank)
BL=4
CK
tRC
/S
tRAS tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
X Y X
A10
X
X
BA
tWR D D D D
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 31 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
WRITE CYCLE (dual bank)
BL=4
CK
tRC
/S
tRAS tRRD tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
Xa Y Xb Y
A10
Xa
Xb
BA
tWR tWR Db Db Db Da Da Da Da Db
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 32 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
READ CYCLE (single bank)
BL=4, CL=3
CK
tRC
/S
tRAS tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
X Y X
A10
X
X
BA
Q Q Q Q
DQ
tRAC
tCAC
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 33 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
READ CYCLE (dual bank)
BL=4, CL=3
CK
tRC
/S
tRAS tRRD tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
Xa Y Xb Y Xa
A10
Xa
Xb
Xa
BA
Qa tCAC tRAC tRAC Qa Qa Qa Qb Qb Qb Qb
DQ
tCAC
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 34 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
WRITE to READ (single bank)
BL=4, CL=3
CK
/S
tRAS
/RAS
tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
X Y Y
A10
X
BA
D D D D tCAC Q Q Q Q
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 35 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
WRITE to READ (dual bank)
BL=4, CL=3
CK
tRC
/S
tRAS tRRD tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
Xa Y Xb Y Xa
A10
Xa
Xb
Xa
BA
tWR Da Da Da Da tCAC Qb Qb Qb Qb
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 36 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
READ to WRITE (single bank)
BL=4, CL=3
CK
/S
tRAS
/RAS
tRCD
/CAS
/WE
CKE
for output diable
DQMB 0-7 A0-9
X Y Y
A10
X
BA
tWR Q tCAC tRAC Q D D D D
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 37 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
READ to WRITE (dual bank)
BL=4, CL=3
CK
tRC
/S
tRAS tRRD tRP tRAS
/RAS
tRCD tRCD
/CAS
/WE
CKE
for output disable
DQMB 0-7 A0-9
Xa Y Xb Y Xa
A1 0 BA
Xa
Xb
Xa
tWR
DQ
tCAC tRAC
Qa
Qa
Db
Db
Db
Db
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 38 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
WRITE with AUTO-PRECHARGE
BL=4
CK
tRC
/S
tWR + tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
X Y X
A10
X
X
BA
D D D D
DQ
internal precharge starts this timing depends on BL
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 39 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
READ with AUTO-PRECHARGE
BL=4, CL=3
CK
tRC
/S
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQMB 0-7 A0-9
X Y X
A10
X
X
BA
Q tCAC tRAC internal precharge starts @CL=3, BL=4 this timing depends on CL and BL Q Q Q
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 40 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
AUTO-REFRESH
CK
tRC
/S
tRP
/RAS
/CAS
/WE
CKE
DQMB 0-7 A0-9
A10
BA
DQ
if any bank is active, it must be precharged
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 41 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
SELF-REFRESH ENTRY
CK
/S
tRP
/RAS
/CAS
/WE
CKE
DQMB 0-7 A0-9
A10
BA
DQ
if any bank is active, it must be precharged
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 42 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
SELF-REFRESH EXIT
CK
/S
NOP or DESEL
/RAS
/CAS
/WE
tRC
CKE
DQMB 0-7 A0-9
X
A10
X
BA
DQ
internal CLK re-start
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 43 / 44 )
Aug.8.1996
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CWZTJ-12,-15
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
MODE REGISTER SET
BL=4, CL=3
CK
/S
tRP tRSC tRCD
/RAS
/CAS
/WE
CKE
DQMB 0-7 A0-9
mode X Y
A10
X
BA
Q tCAC tRAC if any bank is active, it must be precharged Q Q
DQ
MIT-DS-0053-0.2
MITSUBISHI ELECTRIC ( 44 / 44 )
Aug.8.1996

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